With growing technology, the requirement of the dimension of semiconductor process becomes smaller and more complex, especially in processes of ultra large-scale integration circuits. Short-circuit problems come along with the smaller critical dimension among wires, and seriously influence the yield rate and the reliability of the integration circuits. Especially in the complex integration circuits, wires and contacts made by etching and deposition (for example, bit-line contacts) often have short-circuit problems just because slight inaccuracy occurs when the process window is insufficient during manufacturing process.
FIG. 1 shows a top view of the wires and bit-line contacts of the prior art. FIG. 1 shows the relative locations of gates 103, wires 105 and bit-line contacts 101. The schematic diagram of I–I′ section is shown in FIG. 2. FIG. 2 illustrates the wires and bit-line contacts of the prior art. In FIG. 2, an insulation layer 203, which has a predetermined opening, is on the semiconductor substrate 201, and the conductive layer 205 is disposed in the opening. As shown in FIG. 2, there are three wires 105 created by a metallic deposition process. Two of the wires 105 are connected to the conductive layer 205 respectively. The short-circuit problem usually happens after the wires 105 have been deposited if an improper etching process causes an over-scale trench (Illustrated in FIG. 2).